In-line semiconductor package



FIG. 1 is a top, front and left side perspective view of an in-line semiconductor package showing my new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a rear elevational view thereof;

FIG. 6 is a left side elevational view thereof;

FIG. 7 is a right side elevational view thereof;

FIG. 8 is a top, front and left side perspective view of an in-line semiconductor package showing a second embodiment of my new design;

FIG. 9 is a top plan view thereof;

FIG. 10 is a front elevational view thereof;

FIG. 11 is a bottom plan view thereof;

FIG. 12 is a rear elevational view thereof;

FIG. 13 is a right side elevational view thereof, the left side being a mirror image;

FIG. 14 is a top, front and left side perspective view of an in-line semiconductor package showing a third embodiment of my new design;

FIG. 15 is a bottom, left and rear perspective view thereof;

FIG. 16 is a top, front and left side perspective view of an in-line semiconductor package showing a fourth embodiment of my new design;

FIG. 17 is a bottom, left and rear perspective view thereof;

FIG. 18 is a top, front and left side perspective view of an in-line semiconductor package showing a fifth embodiment of my new design;

FIG. 19 is a bottom, left and rear perspective view thereof;

FIG. 20 is a right side elevational view of the third, fourth and fifth embodiments of my new design. 

The ornamental design for a in-line semiconductor package, as shown and described. 